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CS5231-3 500 mA, 3.3 V Linear Regulator with Auxiliary Control
The CS5231-3 combines a three-terminal linear regulator with circuitry controlling an external PFET transistor thus managing two input supplies. The part provides a 3.3 V regulated output either from the main 5.0 V supply or a 3.3 V auxiliary that switches on when the 5.0 V supply is not present. This delivers constant, uninterrupted power to the load. The CS5231-3 meets Intel's "Instantly Available" power requirements which follows from the "Advanced Configuration and Power Interface" (ACPI) standards developed by Intel, Microsoft and Toshiba. The CS5231-3 linear regulator provides a fixed 3.3 V output at 500 mA with an overall accuracy of 2.0%. The internal NPN-PNP composite pass transistor provides a low dropout voltage and requires less supply current than a straight PNP design. Full protection with both current limit and thermal shutdown is provided. Designed for low reverse current, the IC prevents excessive current from flowing from VOUT to either VIN or ground when the regulator input voltage is lower than the output voltage. The CS5231-3 can be used to provide power to an ASIC on a PCI Network Interface Card (NIC). When the system enters a Sleep State and the 5.0 V input drops below 4.4 V, the AuxDrv control signal on the CS5231-3 is activated turning on the external PFET. This switches the supply source from the 5.0 V input to the 3.3 V input through the PFET, guaranteeing a constant 3.3 V output to the ASIC that is "glitch free." The CS5231-3 is available in two package types: the D2PAK-5 (TO263) package and the SOIC-8 4-Lead-fused (DF) package. Other applications include desktop computers, power supplies with multiple input sources and PCMCIA/PCI interface cards.
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D2PAK-5 DP SUFFIX CASE 936AC 1 5 8 1 SOIC-8 DF SUFFIX CASE 751
PIN CONNECTIONS AND MARKING DIAGRAMS
D2PAK-5 Pin 1. No Connect 2. VIN 3. GND 4. VOUT 5. AuxDrv Tab = GND
CS5231-3 AWLYWW
1 1 SOIC-8 8 5231- ALYW3
NC GND GND VIN
AuxDrv GND GND VOUT
* Linear Regulator - 3.3 V 2.0% Output Voltage - 3.0 mA Quiescent Current @ 500 mA - Fast Transient Response - Current Limit Protection - Thermal Shutdown with Hysteresis - 450 mA Reverse Output Current * System Power Management - Auxiliary Supply Control - "Glitch Free" Transition Between Two Supplies * Internally Fused Leads in SOIC-8 Package
A WL, L YY, Y WW, W
= Assembly Location = Wafer Lot = Year = Work Week
ORDERING INFORMATION
Device CS5231-3GDP5 CS5231-3GDPR5 CS5231-3GDF8 CS5231-3GDFR8 Package D2PAK-5 D2PAK-5 SOIC-8 SOIC-8 Shipping 50 Units/Rail 750 Tape & Reel 95 Units/Rail 2500 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2004
1
January, 2004 - Rev. 5
Publication Order Number: CS5231-3/D
CS5231-3
VOUT VIN
10 kW
50 kW
Internal Bias Current Limit
AuxDrv
-
VIN UV Comparator
Error Amp Shutdown
+
Bandgap Reference
GND Thermal Shutdown
ABSOLUTE MAXIMUM RATINGS*
Rating Maximum Operating Junction Temperature Storage Temperature Range Lead Temperature Soldering: ESD Damage Threshold (Human Body Model) 1. 60 second maximum above 183C. *The maximum package power dissipation must be observed. Reflow: (SMD styles only) (Note 1) Value 150 -65 to +150 230 peak 2.0 Unit C C C kV
ABSOLUTE MAXIMUM RATINGS
Pin Name IC Power Input Output Voltage Auxiliary Drive Output IC Ground Pin Symbol VIN VOUT AuxDrv GND VMAX 14 V 6.0 V 14 V N/A VMIN -0.3 V -0.3 V -0.3 V N/A ISOURCE 100 mA Internally Limited 10 mA N/A ISINK Internally Limited 100 mA 50 mA N/A
+
VREF
Figure 1. Block Diagram
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CS5231-3
ELECTRICAL CHARACTERISTICS (0C < TA < 70C; 0C < TJ < 125C; 4.75 V VCC < 6.0 V; COUT 10 mF with
ESR < 1.0 W, IOUT = 10 mA; unless otherwise specified.) Characteristic Linear Regulator Output Voltage Line Regulation Load Regulation Ground Current Reverse Current Current Limit Thermal Shutdown Thermal Shutdown Hysteresis Auxiliary Drive Upper VIN Threshold Lower VIN Threshold VIN Threshold Hysteresis Output Low Voltage Output Low Peak Voltage AuxDrv Current Limit Response Time Pull-Up/Down Resistance Increase VIN until regulator turns on and AuxDrv drives high Decrease VIN until regulator turns off and AuxDrv drives low - IAuxDrv = 100 mA, 1.0 V < VIN < 4.5 V Increase VIN from 0V to 1.0 V. Record peak AuxDrv output voltage VAuxDrv = 1.0 V; VIN = 4.0 V Step VIN from 5.0 V to 4.0 V, measure time for VAuxDrv to drive low. Note 2 VIN = 0 V and VIN > 4.7 V. 4.35 4.25 75 - - 0.5 - 5.0 4.5 4.4 100 0.1 0.65 6.0 1.0 10 4.65 4.55 125 0.4 0.9 25 10 25 V V mV V V mA ms kW 10 mA < IOUT < 500 mA. IOUT = 10mA; VIN = 4.75 V to 6.0 V VIN = 5.0 V; IOUT = 10 mA to 500 mA IOUT = 10 mA IOUT = 500 mA VIN = 0 V, VOUT = 3.3 V 0 V < VOUT < 3.2 V Note 2 Note 2 3.234 (- 2%) - - - - - 0.55 150 - 3.3 1.0 5.0 2.0 3.0 0.45 0.85 180 25 3.366 (+ 2%) 5.0 15 3.0 6.0 1.0 1.2 210 - V mV mV mA mA mA A C C Test Conditions Min Typ Max Unit
2. Guaranteed by design, not 100% production tested. Thermal shutdown is 100% functionally tested at wafer probe.
PACKAGE PIN DESCRIPTION
Package Lead # D2PAK-5 1 2 3, Tab 4 5 SOIC-8 1 4 2, 3, 6, 7 5 8 Lead Symbol NC VIN GND VOUT AuxDrv No connection. Input voltage. Ground and IC substrate connection. Regulated output voltage. Output used to control an auxiliary supply voltage. This lead is driven low if VIN is less than 4.5 V, and is otherwise pulled up to VIN through an internal 10 kW resistor. Function
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CS5231-3
TYPICAL PERFORMANCE CHARACTERISTICS
3.302 IOUT = 10 mA 1.2 125C 1.0 3.300 IOUT = 500 mA 3.298 Load Regulation (mV) Output Voltage (V) 0.8 0.6 0.4 0.2 0C 0 0 20 40 60 80 100 Junction Temperature (C) 120 0 0.2 IOUT (A) 0.4
27C
3.296
Figure 2. Output Voltage vs. Junction Temperature
Figure 3. Line Regulation vs. IOUT Over Temperature
1.2 125C Load Regulation (mV) Reverse Current (mA) 1.0 0.8 0.6 0.4 27C 0.2 0C 0.0 0.0 0.2 IOUT (A) 0.4 0 20 40 60 80 Junction Temperature (C) 100 120 360 390
380
370
Figure 4. Load Regulation vs. IOUT Over Temperature
Figure 5. Reverse Current vs. Junction Temperature
4.52 125C 3 VIN Threshold Voltage (V) 27C VOUT (V) 2 0C 1 4.50 4.48 4.46 4.44 4.42 4.40 0 0.0 0.2 0.4 IOUT (A) 0.6 0.8 1.0 4.38 0 20 VIN Turn-Off Threshold VIN Turn-On Threshold
40 60 80 100 Junction Temperature (C)
120
140
Figure 6. VOUT vs. IOUT Over Junction Temperature
Figure 7. VIN Thresholds vs. Junction Temperature
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CS5231-3
1000 2.6 2.4 2.2 2.0 1.8 1.6 0.0 Stable Region TJ = 25C 100
Ground Current (mA)
TJ = 27C IGND @ 27C
TJ = 125C IGND @ 125C 0.2 Load Current (A) 0.4 10 0 1.0 2.0 3.0 4.0 5.0 Capacitance ESR (W) 6.0 7.0
Figure 8. Ground Current vs. Load Current
Capacitance (mF)
TJ = 0C IGND @ 0C
Figure 9. Region of Stable Operation
5.0 4.8 Current Limit (mA) VOUT
3.4
3.3 CIN = 33 mF COUT = 33 mF VIN = 5.00 V
4.6
3.2
4.4 IOUT (mA)
4.2 4.0 0 20 40 60 80 100 Temperature (C) 120 140
500
10 Time, 5.0 ms per division
Figure 10. AuxDrv Current Limit vs. Junction Temperature
Figure 11. Transient Response
5.0 V PCI C1 33 mF
VIN GND
VOUT
CS5231-3
AuxDrv
M1 3.3 V VAUX C1 33 mF C3 33 mF
ASIC VDD
* indicates PFET body diode
Figure 12. Application Circuit
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CS5231-3
APPLICATION INFORMATION THEORY OF OPERATION The CS5231-3 is a fixed 3.3 V linear regulator that contains an auxiliary drive control feature. When VIN is greater than the typical 4.5 V threshold, the IC functions as a linear regulator. It provides up to 500 mA of current to a load through a composite PNP-NPN pass transistor. An output capacitor greater than 10 mF with equivalent series resistance less than 1.0 W is required for compensation. More information is provided in the Stability Considerations section. The CS5231-3 provides an auxiliary drive feature that allows a load to remain powered even if the VIN supply for the IC is absent. An external p-channel FET is the only additional component required to implement this function if an auxiliary power supply is available. The PFET gate is connected to the AuxDrv lead. The PFET drain is connected to the auxiliary power supply, and the PFET source is connected to the load. The polarity of this connection is very important, since the PFET body diode will be connected between the load and the auxiliary supply. If the PFET is connected with its drain to the load and its source to the supply, the body diode will be forward-biased if the auxiliary supply is turned off. This will result in the linear regulator providing current to everything on the auxiliary supply rail. The AuxDrv lead is internally connected to a 10 kW resistor and to a saturating NPN transistor that acts as a switch. If the VIN supply is off, the AuxDrv output will connect the PFET gate to ground through the 10 kW resistor, and the PFET will conduct current to the load. As the VIN supply begins to rise, the AuxDrv lead will also rise until it reaches a typical voltage of about 650 mV. The NPN transistor connected to the AuxDrv lead will saturate at this point, and the gate of the PFET will be pulled down to a typical voltage of about 100 mV. The PFET will continue to conduct current to the load. The VIN supply voltage will continue to rise, but the linear regulator output is disabled until VIN reaches a typical threshold of 4.5 V. During this time, the load continues to be powered by the auxiliary driver. Once the 4.5 V VIN threshold is reached, the saturating NPN connected to the AuxDrv lead turns off. The on-chip 10 kW pull-up resistor will pull the PFET gate up to VIN, thus turning the PFET off. The linear regulator turns on at the same time. An external compensation capacitor is required for the linear regulator to be stable, and this capacitance also serves as a charge reservoir to minimize any "glitching" that might result during the supply changeover. Hysteresis is present in the AuxDrv circuitry, requiring VIN to drop by 100 mV (typical) after the linear regulator is providing power to the load before the AuxDrv circuitry can be re-enabled.
VIN
VOUT
VAUXDRV
IOUT = STARTUP 375 mA
Figure 13. Initial Power-Up, VAUX Not Present ROUT = 8.8 W
VIN
VOUT
VAUXDRV
IOUT = 375 mA VAUX = 3.30 V
Figure 14. Power-Up, VAUX = 3.3 V. Note the "Oscillatory Performance" as the Linear Regulator Changes the VOUT Node. IOUT y RDS(ON) 9 130 mV
VIN
VOUT VAUXDRV
IOUT = 375 mA VAUX = 3.30
Figure 15. Power-Down, VAUX = 3.3 V. Again, Note DV = I RDS(ON) 9 130 mV
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CS5231-3
VIN VIN VOUT VOUT
VAUXDRV
VAUXDRV
IOUT = 375 mA VAUX = 3.135 V
IOUT = 375 mA VAUX = 3.465
Figure 16. Power-Up, VAUX = 3.135 V. The "Oscillatory Performance" Mode Lasts Longer Because the Difference Between VAUX and 3.3 is Greater
Figure 19. Power-Down, VAUX = 3.465 V
VIN
VOUT VAUXDRV
IOUT = 375 mA VAUX = 3.135
Figure 17. Power-Down, VAUX = 3.135 V. The Difference in Voltage is Now IOUT y RDS(ON) Plus the Difference in Supply Voltages (3.3 - VAUX)
STABILITY CONSIDERATIONS The output capacitor helps determine three main characteristics of a linear regulator: startup, transient response and stability. Startup is affected because the output capacitor must be charged. At initial startup, the VIN supply may not be present, and the output capacitor will be charged through the PFET. The PFET will initially provide current to the load through its body diode. The diode will act as a voltage follower until sufficient voltage is present to turn the FET on. Since most commercial power supplies have a fairly low ramp rate, charging through the body diode should effectively limit in-rush current to the capacitor. During normal operation, transient load current requirements will be satisfied from the charge stored in the output capacitor until either the linear regulator or the auxiliary supply can respond. Larger values of capacitance will improve transient response, but will also cost more. A linear regulator will respond within microseconds, where an external power supply may take milliseconds to react. The output capacitance will provide the difference in current until this occurs. The result will be an instantaneous voltage change at the output. This change is the product of the current change and the capacitor ESR:
DVOUT + DILOAD ESR
VIN
VOUT
VAUXDRV
IOUT = 375 mA VAUX = 3.465
Figure 18. Power-Up, VAUX = 3.465 V. IOUT y RDS(ON) is Compensated By Higher Value of VAUX
This limitation directly affects load regulation. Capacitor ESR must be minimized if output voltage must be maintained within tight tolerances. In such a case, it is often advisable to use a parallel network of different types of capacitors. For example, electrolytic capacitors provide high charge storage capacity in a small size, while tantalum capacitors have low ESR. The parallel combination will result in a high capacity, low ESR network. It is also important to physically locate the capacitance network close to the load, and to connect the network to the load with wide PC board traces to minimize the metal resistance.
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CS5231-3
The CS5231-3 has been carefully designed to be stable for output capacitances greater than 10 mF with equivalent series resistance less than 1.0 W. While careful board layout is important, the user should have a stable system if these constraints are met. A graph showing the region of stability for the CS5231-3 is included in the "Typical Performance Characteristics" section of this datasheet. INPUT CAPACITORS AND THE VIN THRESHOLDS A capacitor placed on the VIN pin will help to improve transient response. During a load transient, the input capacitor serves as a charge "reservoir," providing the needed extra current until the external power supply can respond. One of the consequences of providing this current is an instantaneous voltage drop at VIN due to capacitor ESR. The magnitude of the voltage change is again the product of the current change and the capacitor ESR. It is very important to consider the maximum current step that can exist in the system. If the change in current is large enough, it is possible that the instantaneous voltage drop on VIN will exceed the VIN threshold hysteresis, and the IC will enter a mode of operation resembling an oscillation. As the part turns on, the output current IOUT will increase, reaching current limit during initial charging. Increasing IOUT results in a drop at VIN such that the shutdown threshold is reached. The part will turn off, and the load current will decrease. As IOUT decreases, VIN will rise and the part will turn on, starting the cycle all over again. This oscillatory operation is most likely at initial start-up when the output capacitance is not charged, and in cases where the ramp-up of the VIN supply is slow. It may also occur during the power transition when the regulator turns on and the PFET turns off. A 15 ms delay exists between turn-on of the regulator and the AuxDrv pin pulling the gate of the PFET high. This delay prevents "chatter" during the power transitions. During this interval, the linear regulator will attempt to regulate the output voltage as 3.3 V. If the output voltage is significantly below 3.3 V, the IC will go into current limit while trying to raise VOUT. It is a short-lived phenomenon and is mentioned here to alert the user that the condition can exist. It is typically not a problem in applications. Careful choice of the PFET switch with respect to RDS(ON) will minimize the voltage drop which the output must charge through to return to a regulated state. More information is provided in the section on choosing the PFET switch. If required, using a few capacitors in parallel to increase the bulk charge storage and reduce the ESR should give better performance than using a single input capacitor. Short, straight connections between the power supply and VIN lead along with careful layout of the PC board ground plane will reduce parasitic inductance effects. Wide VIN and VOUT traces will reduce resistive voltage drops. CHOOSING THE PFET SWITCH The choice of the external PFET switch is based on two main considerations. First, the PFET should have a very low turn-on threshold. Choosing a switch transistor with VGS(ON) 1.0 V will ensure the PFET will be fully enhanced with only 3.3 V of gate drive voltage. Second, the switch transistor should be chosen to have a low RDS(ON) to minimize the voltage drop due to current flow in the switch. The formula for calculating the maximum allowable on-resistance is
V * VOUT(MIN) RDS(ON)MAX + AUX(MIN) 1.5 IOUT(MAX)
where VAUX(MIN) is the minimum value of the auxiliary supply voltage, VOUT(MIN) is the minimum allowable output voltage, IOUT(MAX) is the maximum output current and 1.5 is a "fudge factor" to account for increases in RDS(ON) due to temperature. OUTPUT VOLTAGE SENSING It is not possible to remotely sense the output voltage of the CS5231-3 since the feedback path to the error amplifier is not externally available. It is important to minimize voltage drops due to metal resistance of high current PC board traces. Such voltage drops can occur in both the supply traces and the return traces. The following board layout practices will help to minimize output voltage errors: * Always place the linear regulator as close to both load and output capacitors as possible. * Always use the widest possible traces to connect the linear regulator to the capacitor network and to the load. * Connect the load to ground through the widest possible traces. * Connect the IC ground to the load ground trace at the point where it connects to the load. CURRENT LIMIT The CS5231-3 has internal current limit protection. Output current is limited to a typical value of 850 mA, even under output short circuit conditions. If the load current drain exceeds the current limit value, the output voltage will be pulled down and will result in an out of regulation condition. The IC does not contain circuitry to report this fault. THERMAL SHUTDOWN The CS5231-3 has internal temperature monitoring circuitry. The output is disabled if junction temperature of the IC reaches 180C. Thermal hysteresis is typically 25C and allows the IC to recover from a thermal fault without the
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CS5231-3
need for an external reset signal. The monitoring circuitry is located near the composite PNP-NPN output transistor, since this transistor is responsible for most of the on-chip power dissipation. The combination of current limit and thermal shutdown will protect the IC from nearly any fault condition. REVERSE CURRENT PROTECTION During normal system operation, the auxiliary drive circuitry will maintain voltage on the VOUT pin when VIN is absent. IC reliability and system efficiency are improved by limiting the amount of reverse current that flows from VOUT to ground and from VOUT to VIN. Current flows from VOUT to ground through the feedback resistor divider that sets up the output voltage This resistor can range in value from 6.0 kW to about 10 kW, and roughly 500 mA will flow in the typical case. Current flow from VOUT to VIN will be limited to leakage current after the IC shuts down. On-chip RC time constants are such that the output transistor should be turned off well before VIN drops below the VOUT voltage. CALCULATING POWER DISSIPATION AND HEATSINK REQUIREMENTS Most linear regulators operate under conditions that result in high on-chip power dissipation. This results in high junction temperatures. Since the IC has a thermal shutdown feature, ensuring the regulator will operate correctly under normal conditions is an important design consideration. Some heatsinking will usually be required. Thermal characteristics of an IC depend on four parameters: ambient temperature (TA in C), power dissipation (PD in watts), thermal resistance from the die to the ambient air (qJA in C per watt) and junction temperature (TJ in C). The maximum junction temperature is calculated from the formula below:
TJ(MAX) + TA(MAX) ) (qJA PD(MAX))
(qJC), case-to-heatsink thermal resistance (qCS) and heatsink-to-air thermal resistance (qSA). The resulting equation for junction-to-air thermal resistance is
qJA + qJC ) qCS ) qSA
The value of qJC both packages of the CS5231-3 are provided in the Packaging Information section of this data sheet. The value of qCS can be considered zero, since heat is conducted out of the D2PAK package by the IC leads and the tab, and out of the SOIC-8 package by its IC leads that are soldered directly to the PC board. Modification of qSA is the primary means of thermal management. For surface mount components, this means modifying the amount of trace metal that connects to the IC. The thermal capacity of PC board traces is dependent on how much copper area is used, whether or not the IC is in direct contact with the metal, whether or not the metal surface is coated with some type of sealant, and whether or not there is airflow across the PC board. The chart provided below shows heatsinking capability of a square, single sided copper PC board trace. The area is given in square millimeters, and it is assumed there is no airflow across the PC board.
70 60 50 40 30 20 10 0
Maximum ambient temperature and power dissipation are determined by the design, while qJA is dependent on the package manufacturer. The maximum junction temperature for operation of the CS5231-3 within specification is 150C. The maximum power dissipation of a linear regulator is given as
PD(MAX) + (VIN(MAX) * VOUT(MIN)) (ILOAD(MAX) ) VIN(MAX)) IGND(MAX)
Thermal Resistance, CW
0
2000 4000 PC Board Trace Area (mm2)
6000
Figure 20. Thermal Resistance Capability of Copper PC Board Metal Traces
where IGND(MAX) is the IC bias current. It is possible to change the effective value of qJA by adding a heatsink to the design. A heatsink serves in some manner to raise the effective area of the package, thus improving the flow of heat from the package into the surrounding air. Each material in the path of heat flow has its own characteristic thermal resistance, all measured in C per watt. The thermal resistances are summed to determine the total thermal resistance between the die junction and air. There are three components of interest: junction-to-case thermal resistance
TYPICAL D2PAK PC BOARD HEATSINK DESIGN A typical design of the PC board surface area needed for the D2PAK package is shown on page 11. Calculations were made assuming VIN(MAX) = 5.25 V, VOUT(MIN) = 3.266 V, IOUT(MAX) = 500 mA, IGND(MAX) = 5.0 mA and TA = 70C.
PD + (5.25 V * 3.266 V) 0.5 A ) (5.25 V)(0.005 A) + 1018 mW
Maximum temperature rise
DT + TJ(MAX) * TA + 150C * 70C + 80C
qJA(worst case) + DT PD + 80C 1.018 W + 78.56C W
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First, we determine the need for heatsinking. If we assume the maximum qJA = 50 C/W for the D2PAK, the maximum temperature rise is found to be
DT + PD qJA + 1.018 W 50C W + 50.9C
IOUT (mA) 600 500 400 300 200 100 0
This is less than the maximum specified operating junction temperature of 125C, and no heatsinking is required. Since the D2PAK has a large tab, mounting this part to the PC board by soldering both tab and leads will provide superior performance with no PC board area penalty. TYPICAL FUSED SOIC-8 DESIGN We first determine the need for a heat sink for the SOIC-8 package at a load of 500 mA. Using the dissipation from the D2PAK example of 1018 mW and the qJA of the SOIC-8 package of 110C/W gives a temperature rise of 112C. Adding this to an ambient temperature of 70C gives 182C junction temperature. This is an excessive temperature rise but it can be reduced by adding additional cooling in the form of added surface area of copper on the PCB. Using the relationship of maximum temperature rise of
DTJA + TJ(MAX) * TA + 150C * 70C + 80C
5
6
7
8
9 10 VIN (Volts)
11
12
13
14
Figure 21. Demo Board Output Current Derating vs. VIN The VIN Connection
The VIN connection is denoted as such on the PC board. The maximum input voltage to the IC is 14 V before damage to the IC is possible. However, the specification range for the IC is 4.75 V < VIN < 6.0 V.
The GND Connection
We calculate the thermal resistance allowed from junction to air:
qJA(worst case) + DTJA PD + 80C 1.018 W + 79.6C W
The thermal resistance from the die to the leads (case) is 25C/W. Subtracting these two numbers gives the allowable thermal resistance from case to ambient:
qCA + qJA * qJC + 79.6C W * 25C W + 54.6C W
The GND connection ties the IC power return to two turret pins. The extra turret pin provides for connection of multiple instrument grounds to the demonstration board.
The AuxDrv Connection
The thermal resistance of this copper area will be 54.6C/W. We now look at Figure 20 and find the PCB trace area that will be less than 54.5C/W. Examination shows that 750 mm2 of copper will provide cooling for this part. This would be the SOIC-8 part with the center 4 ground leads soldered to pads in the center of a copper area about 27 mm x 27 mm. A lower dissipation or the addition of air-flow could result in a smaller required surface area. DESCRIPTION The CS5231-3 application circuit has been implemented as shown in the following pages. The schematic, bill of materials and printed circuit board artwork can be used to build the circuit. The design is very simple and consists of two capacitors, a p-channel FET and the CS5231-3. Five turret pins are provided for connection of supplies, meters, oscilloscope probes and loads. The CS5231-3 power supply management solution is implemented in an area less than 1.5 square inches. Due to the simplicity of the design, output current must be derated if the CS5231-3 is operated at VIN voltages greater than 7.0 V. Figure 21 provides the derating curve on a maximum power dissipation if heatsink is added. Operating at higher power dissipation without CS5231-3 heatsink may result in a thermal shutdown condition.
The AuxDrv lead of the CS5231-3 is connected to the gate of the external PFET. This connection is also brought to a turret pin to allow easy connection of an oscilloscope probe for viewing the AuxDrv waveforms.
The VAUX Connection
The VAUX turret pin provides a connection point between an external 3.3 V supply and the PFET drain.
The VOUT Connection
The VOUT connection is tied to the VOUT lead of the CS5231-3 and the PFET source. This point provides a convenient point at which some type of lead may be applied.
VIN TP1 C1 GND TP2 TP3 GND VIN VOUT CS5231-3 AuxDrv Q1 TP4 VAUX TP6 AuxDrv U1 TP5
+3.3 V
C2
Figure 22. Application Circuit Schematic
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CS5231-3
PC Board Layout Artwork Temperature Performance
The PC Board is a single layer copper design. The layout artwork is reproduced at actual size below.
2"
The graph below shows thermal performance for the CS5231-3 across the normal operating output current range.
55 50 Package Temperature (C) 45 40 35 30 25 20
1.8"
Figure 23. Top Copper Layer
0 50
2"
100 150 200 250 300 350 400 450 500 Load Current (mA)
VIN 5.0 V
AUX.DRV
Figure 25. Package Temperature vs. Load Current (VIN = 5.0 V, TA = 235C) PFET RDS(ON) Performance
1.8"
AUX 3.3 V VOUT 3.3 V GND
GND
The graph provided below show typical RDS(ON) performance for the PFET. The data is provided as VDS vs IOUT for different values of VAUX.
160 140 VAUX = 3.135 V VAUX = 3.300 V
Figure 24. Top Silk Screen Layer
120
Test Description
The startup and supply transition waveforms shown in Figures 13 through 19 were obtained using the application circuit board with a resistive load of 8.8 W. This provides a DC load of 375 mA when the regulated output voltage is 3.3 V. A standard 2.0 A bench supply was used to provide power to the application circuit. The transient response waveforms shown in the Typical Performance Characteristics section were obtained by switching a 6.3 W resistor across the output.
100 VDS (mV) 80 60 40 20 0 0 100 200 300 400 500 IOUT (mA) VAUX = 3.465 V
Figure 26. PFET VDS vs. IOUT
Ref des C1, C2 Q1 U1 T1-T6
Description
Part Number
Manufacturer AVX Corp ON Semiconductor ON Semiconductor Newark Electronics
33 mF, 16 V tantalum capacitors p-channel FET transistor
TAJD336K016
MGSF1P02ELT1 CS5231-3DPS 40F6023
Linear regulator with auxiliary Turret pins
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APPLICATIONS CIRCUIT BILL OF MATERIALS
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CS5231-3
PACKAGE DIMENSIONS
D2PAK-5 DP SUFFIX CASE 936AC-01 ISSUE O
For D2PAK Outline and Dimensions - Contact Factory
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CS5231-3
PACKAGE DIMENSIONS
SOIC-8 DF SUFFIX CASE 751-07 ISSUE AA
-X- A
8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
B
1 4
S
0.25 (0.010)
M
Y
M
-Y- G C -Z- H D 0.25 (0.010)
M SEATING PLANE
K
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
SOLDERING FOOTPRINT
1.52 0.060 7.0 0.275 4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
Figure 27. SOIC-8
PACKAGE THERMAL DATA Parameter RqJC RqJA Typical Typical D2PAK-5 2.5 10-50* SOIC-8 25 110 Unit C/W C/W
*Depending on thermal properties of substrate. RqJA = RqJC + RqCA.
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CS5231-3
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